[all-commits] [llvm/llvm-project] decf38: [RISCV] Teach targetShrinkDemandedConstant to hand...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: decf385c270ed814ac00331410b34fdea4e0b2b1
      https://github.com/llvm/llvm-project/commit/decf385c270ed814ac00331410b34fdea4e0b2b1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-17 (Sun, 17 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/legalize-fneg.ll
    M llvm/test/CodeGen/RISCV/rv64i-demanded-bits.ll

  Log Message:
  -----------
  [RISCV] Teach targetShrinkDemandedConstant to handle OR and XOR.

We were only handling AND before, but SimplifyDemandedBits can
also call it for OR and XOR.