[all-commits] [llvm/llvm-project] ee6267: [RISCV] Remove Gather/Scatter Opt from the O0 pipe...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ee6267c4431353f114889e84c9fa1accd890de34
      https://github.com/llvm/llvm-project/commit/ee6267c4431353f114889e84c9fa1accd890de34
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-17 (Sun, 17 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O0-pipeline.ll

  Log Message:
  -----------
  [RISCV] Remove Gather/Scatter Opt from the O0 pipeline.


  Commit: 73f766ca9a08d570c5831b815902189aa5568f78
      https://github.com/llvm/llvm-project/commit/73f766ca9a08d570c5831b815902189aa5568f78
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-17 (Sun, 17 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp

  Log Message:
  -----------
  [RISCV] Remove unnecessary use of IRBuilder from RISCVCodeGenPrepare.

We're creating single instruction to replace another instruction.
We can insert using the InsertBefore operand of the constructor.
Then copy the debug location.


  Commit: 8cc483099a0431f3dc8181b4af0f5aeba1b97ba9
      https://github.com/llvm/llvm-project/commit/8cc483099a0431f3dc8181b4af0f5aeba1b97ba9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-17 (Sun, 17 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
    M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
    M llvm/test/CodeGen/RISCV/O3-pipeline.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare-asm.ll
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

  Log Message:
  -----------
  [RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))

If X is known positive by a dominating condition, we can fill in
ones into the upper bits of C1 if that would allow it to become an
simm12 allowing the use of ANDI.

This pattern often occurs in unrolled loops where the induction
variable has been widened.

To get the best benefit from this, I had to move the pass above
ConstantHoisting which is in addIRPasses. Otherwise the AND constant
is often hoisted away from the AND.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D129888


Compare: https://github.com/llvm/llvm-project/compare/53b90dd372c4...8cc483099a04