[all-commits] [llvm/llvm-project] 1cb741: [DAG] combineShiftAnd1ToBitTest - match "and (srl ...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1cb7416ee3763db5731492fd91013fde331d243e
      https://github.com/llvm/llvm-project/commit/1cb7416ee3763db5731492fd91013fde331d243e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-07-16 (Sat, 16 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/X86/test-vs-bittest.ll

  Log Message:
  -----------
  [DAG] combineShiftAnd1ToBitTest - match "and (srl (not X), C)), 1 --> (and X, 1<<C) == 0" patterns

combineShiftAnd1ToBitTest already matches "and (not (srl X, C)), 1 --> (and X, 1<<C) == 0" patterns, but we can end up with situations where the not is before the shift.

Part of some yak shaving for D127115 to generalise the "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" fold.