[all-commits] [llvm/llvm-project] 450f0b: [RISCV] Add additional tests for D121833. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 450f0bd17b749850c50ce925cb987a5329a656f0
      https://github.com/llvm/llvm-project/commit/450f0bd17b749850c50ce925cb987a5329a656f0
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/shl-demanded.ll

  Log Message:
  -----------
  [RISCV] Add additional tests for D121833. NFC


  Commit: dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434
      https://github.com/llvm/llvm-project/commit/dcfc1fd26f6c2e6ecb1f8f9ae1b77d7b5c30c434
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/AMDGPU/shl.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/RISCV/alu16.ll
    M llvm/test/CodeGen/RISCV/alu8.ll
    M llvm/test/CodeGen/RISCV/shl-demanded.ll
    M llvm/test/CodeGen/Thumb2/LowOverheadLoops/while-loops.ll

  Log Message:
  -----------
  [SelectionDAG][RISCV][AMDGPU][ARM] Improve SimplifyDemandedBits for SHL with variable shift amount.

If we have a variable shift amount and the demanded mask has leading
zeros, we can propagate those leading zeros to not demand those bits
from operand 0. This can allow zero_extend/sign_extend to become
any_extend. This pattern can occur due to C integer promotion rules.

This transform is already done by InstCombineSimplifyDemanded.cpp where
sign_extend can be turned into zero_extend for example.

Reviewed By: spatel, foad

Differential Revision: https://reviews.llvm.org/D121833


Compare: https://github.com/llvm/llvm-project/compare/80dec2ecfffe...dcfc1fd26f6c