[all-commits] [llvm/llvm-project] c0df6b: [RISCV][LSR] Add coverage for ICmpZero with scaled...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0df6bc949afd79a340224a9e120f58451ebe10e
      https://github.com/llvm/llvm-project/commit/c0df6bc949afd79a340224a9e120f58451ebe10e
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll

  Log Message:
  -----------
  [RISCV][LSR] Add coverage for ICmpZero with scaled vscale values

Follow up to 3bc09c7da5 - remove a fixme I forgot to remove, and add test cases showing remaining work.

Note that scaled vscales show up in vectorized code from a couple of sources:
* Element types smaller than vector block size (i.e. everything under i64)
* Unrolling
* LMUL > 1

The largest scaling we can currently have is 256 (e8 in every possible vector register).  More practically useful scales are in the 2-16 range.