[all-commits] [llvm/llvm-project] e32864: [RISCV] Add test case show missed opportunity to t...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e32864b60568316a5fc967086380f44076cd818b
      https://github.com/llvm/llvm-project/commit/e32864b60568316a5fc967086380f44076cd818b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-13 (Wed, 13 Jul 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

  Log Message:
  -----------
  [RISCV] Add test case show missed opportunity to turn slliw+sraiw into slli+srai.

slliw and sraiw have no compressed encodings. slli and srai
do have compressed encodings.

Pre-commit for D129688