[all-commits] [llvm/llvm-project] 5f7641: [RISCV] Modify the custom isel for (add X, imm) us...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5f7641a3be2ed916a6e25a2ad92cfd2b1cd603d1
      https://github.com/llvm/llvm-project/commit/5f7641a3be2ed916a6e25a2ad92cfd2b1cd603d1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-09 (Sat, 09 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/split-offsets.ll

  Log Message:
  -----------
  [RISCV] Modify the custom isel for (add X, imm) used by load/stores.

We have custom isel that tries to select the Lo12 bits using a
separate ADDI that can later folded into the load/store address
by the post-isel peephole.

This patch disables this if the load/store already had a non-zero
offset. A non-zero offset implies that CodeGenPrepare split several
large offsets used by different loads and stores into a common large
offset and multiple small offsets that could be folded. Folding more
of the lo12 bits changes this common offset by increasing the small
offsets. While this can save an instruction to materialize the common
offset, it can also prevent the small offsets from fitting in a
compressed load/store instruction.

Removing this also simplifies the last piece needed to fold the custom
isel for add into SelectAddrRegImm and remove the post-isel peephole.