[all-commits] [llvm/llvm-project] 1ee6ce: GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD

Fri Jul 8 08:55:21 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ee6ce9bad4d7d61e5c6d37ebd5bfa89b91096c6
      https://github.com/llvm/llvm-project/commit/1ee6ce9bad4d7d61e5c6d37ebd5bfa89b91096c6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64InstrAtomics.td
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-load-and-mask.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-zextload.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir
    M llvm/utils/TableGen/CodeGenDAGPatterns.cpp
    M llvm/utils/TableGen/GlobalISelEmitter.cpp

  Log Message:
  -----------
  GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD

SelectionDAG has a target hook, getExtendForAtomicOps, which it uses
in the computeKnownBits implementation for ATOMIC_LOAD. This is pretty
ugly (as is having a separate load opcode for atomics), so instead
allow making use of atomic zextload. Enable this for AArch64 since the
DAG path defaults in to the zext behavior.

The tablegen changes are pretty ugly, but partially helps migrate
SelectionDAG from using ISD::ATOMIC_LOAD to regular ISD::LOAD with
atomic memory operands. For now the DAG emitter will emit matchers for
patterns which the DAG will not produce.

I'm still a bit confused by the intent of the isLoad/isStore/isAtomic
bits. The DAG implementation rejects trying to use any of these in
combination. For now I've opted to make the isLoad checks also check
isAtomic, although I think having isLoad and isAtomic set on these
makes most sense.

  Commit: e9a45d45d0c32a5a5d7d6a55794a5e7785c6a769
      https://github.com/llvm/llvm-project/commit/e9a45d45d0c32a5a5d7d6a55794a5e7785c6a769
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir

  Log Message:
  -----------
  GlobalISel: Allow forming atomic/volatile G_SEXTLOAD

Mirror the change to G_ZEXTLOAD.

  Commit: 13ac4c3de9e0ef5c171f953bf301f87c652bf7ac
      https://github.com/llvm/llvm-project/commit/13ac4c3de9e0ef5c171f953bf301f87c652bf7ac
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp

  Log Message:
  -----------
  GlobalISel: Add buildBoolExtInReg helper

  Commit: 02769f2b3fdebb5066d7a973b171d2873a804560
      https://github.com/llvm/llvm-project/commit/02769f2b3fdebb5066d7a973b171d2873a804560
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/huge-switch.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-intrinsic-min-max.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadd-sat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usub-sat.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-combiner-zext-trunc-crash.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-and-tbnz-tbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-lowering-adjust-icmp-imm.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-sext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-assert-zext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-fp-use-def.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbank-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-br.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-brcond-of-binop.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cbz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-truncstore-atomic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbnz-slt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/tbz-sgt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/arm64-xaluo.ll

  Log Message:
  -----------
  AArch64/GlobalISel: Stop using legal s1 values

As far as I can tell treating s1 values as legal makes no sense. There
are no allocatable 1-bit registers. SelectionDAG legalizes the usual
set of boolean operations to 32-bits, and this should do the
same. This avoids some special case handling in the selector of s1
values, and some extra code to look through truncates.

This makes some code worse at -O0, since nothing cleans up the and 1
the artifact combiner inserts. We could probably add some
non-essential combines or teach the artifact combiner to elide
intermediates betweeen boolean uses and defs.

Compare: https://github.com/llvm/llvm-project/compare/0d7161af89f9...02769f2b3fde