[all-commits] [llvm/llvm-project] 5c45ae: [RISCV] Fix wrong register rename for store value ...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5c45ae4108d3fdd2a00fbe1890316be82e4fa119
      https://github.com/llvm/llvm-project/commit/5c45ae4108d3fdd2a00fbe1890316be82e4fa119
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    M llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir

  Log Message:
  -----------
  [RISCV] Fix wrong register rename for store value during make-compressible optimization

Current implementation will rename both register in store instructions if
we store base address into memory with same base register, it's OK if
the offset is 0, however that is wrong transform if offset isn't 0, give
a smalle example here:

sd      a0, 808(a0)

We should not transform into:

addi    a2, a0, 768
sd      a2, 40(a2)

That should just rename base address like this:

addi    a2, a0, 768
sd      a0, 40(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128876