[all-commits] [llvm/llvm-project] 7b9a3b: [RISCV] Precommit testcase to show wrong result of...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580
      https://github.com/llvm/llvm-project/commit/7b9a3b9d6d98184d3e20c03fceefaac6dc0c3580
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-07-08 (Fri, 08 Jul 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir

  Log Message:
  -----------
  [RISCV] Precommit testcase to show wrong result of make-compressible optimization

Use following example to demo what happened now:

  li      a1, 1
  sd      a1, 800(a0)
  sd      a0, 808(a0) # Store base address into base + offset
  li      a1, 2
  sd      a1, 816(a0)

Current will optimizate into:

  li      a1, 1
  addi    a2, a0, 768
  sd      a1, 32(a2)
  sd      a2, 40(a2) # Wrong replacement for the source register.
  li      a1, 2
  sd      a1, 48(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128875