[all-commits] [llvm/llvm-project] 60d6be: [LegalizeTypes] Replace vecreduce_xor/or/and with ...

[Bradley Smith via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 60d6be5dd3f411cfe1b5392cbbd6131d0ade2faa
      https://github.com/llvm/llvm-project/commit/60d6be5dd3f411cfe1b5392cbbd6131d0ade2faa
  Author: Bradley Smith <bradley.smith at arm.com>
  Date:   2022-07-07 (Thu, 07 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/reduce-and.ll
    M llvm/test/CodeGen/AArch64/reduce-or.ll
    M llvm/test/CodeGen/AArch64/reduce-xor.ll
    M llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

  Log Message:
  -----------
  [LegalizeTypes] Replace vecreduce_xor/or/and with vecreduce_add/umax/umin if not legal

This is done during type legalization since the target representation of
these nodes may not be valid until after type legalization, and after
type legalization the fact that these are dealing with i1 types may be
lost.

Differential Revision: https://reviews.llvm.org/D128996