[all-commits] [llvm/llvm-project] 15c3ba: [AArc64] Legalisation of compares and truncates of...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 15c3ba8a44ab8c12b72a69afdea1c7e80f584643
      https://github.com/llvm/llvm-project/commit/15c3ba8a44ab8c12b72a69afdea1c7e80f584643
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-07 (Thu, 07 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-trunc.ll

  Log Message:
  -----------
  [AArc64] Legalisation of compares and truncates of nxv1i1 types.

Truncates and compares require some changes to generic legalisation functions
to use ElementCount instead of getNumElements.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D129082


  Commit: 6106a767b723134a944ac4f2152c92b140d7a5f4
      https://github.com/llvm/llvm-project/commit/6106a767b723134a944ac4f2152c92b140d7a5f4
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-07 (Thu, 07 Jul 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/test/CodeGen/AArch64/sme-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sme-intrinsics-stores.ll

  Log Message:
  -----------
  [AArch64][SME] Update load/store intrinsics to take predicate corresponding to element size.

Instead of using <vscale x 16 x i1> for all the loads/stores, we now use the appropriate
predicate type according to the element size, e.g.

  ld1b uses <vscale x 16 x i1>
  ld1w uses <vscale x 4 x i1>
  ld1q uses <vscale x 1 x i1>

Reviewed By: kmclaughlin

Differential Revision: https://reviews.llvm.org/D129083


Compare: https://github.com/llvm/llvm-project/compare/b6eeef071290...6106a767b723