[all-commits] [llvm/llvm-project] 5d4f6c: [AArch64][SVE] Zero other lanes when doing OR redu...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d4f6ce22990a48d0d414b94e005ed4816c61261
      https://github.com/llvm/llvm-project/commit/5d4f6ce22990a48d0d414b94e005ed4816c61261
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-06 (Wed, 06 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-vecreduce-fold.ll

  Log Message:
  -----------
  [AArch64][SVE] Zero other lanes when doing OR reduction on unpacked predicate using ptest.

When the predicate vector is unpacked, we cannot assume anything about the
values in the other lanes. We have to make sure we use the correct
predicate where we know that the other lanes have been zeroed.

Reviewed By: RosieSumpter

Differential Revision: https://reviews.llvm.org/D129081