[all-commits] [llvm/llvm-project] e7db82: [AArch64] NFC: Fix name mangling in sve-insert-vec...

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e7db82d701d002240d8ef6bd98d1d221b36eb63e
      https://github.com/llvm/llvm-project/commit/e7db82d701d002240d8ef6bd98d1d221b36eb63e
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-06 (Wed, 06 Jul 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll

  Log Message:
  -----------
  [AArch64] NFC: Fix name mangling in sve-insert-vector.ll


  Commit: 95e08824faba43a4fa052b9366dcea19e2268541
      https://github.com/llvm/llvm-project/commit/95e08824faba43a4fa052b9366dcea19e2268541
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-06 (Wed, 06 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-int-log.ll
    M llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

  Log Message:
  -----------
  [AArch64] Add support for various operations on nxv1i1 types.

The supported operations are:
* Logical operations (and, or, xor, bic)
* Logical reductions (and, or, xor, [us]min, [us]max)
* Conversions to/from svbool_t
* Predicate count (CNTP)

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D128835


Compare: https://github.com/llvm/llvm-project/compare/b484cbbc682c...95e08824faba