[all-commits] [llvm/llvm-project] 1023dd: [LLVM] Add the support for fmax and fmin in atomic...

[Shilei Tian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1023ddaf779015a991cc02d4e61fb29efb767327
      https://github.com/llvm/llvm-project/commit/1023ddaf779015a991cc02d4e61fb29efb767327
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2022-07-06 (Wed, 06 Jul 2022)

  Changed paths:
    M llvm/docs/GlobalISel/GenericOpcode.rst
    M llvm/docs/LangRef.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/include/llvm-c/Core.h
    M llvm/include/llvm/AsmParser/LLToken.h
    M llvm/include/llvm/Bitcode/LLVMBitCodes.h
    M llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
    M llvm/include/llvm/CodeGen/ISDOpcodes.h
    M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
    M llvm/include/llvm/IR/Instructions.h
    M llvm/include/llvm/Support/TargetOpcodes.def
    M llvm/include/llvm/Target/GenericOpcodes.td
    M llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/AsmParser/LLLexer.cpp
    M llvm/lib/AsmParser/LLParser.cpp
    M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
    M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
    M llvm/lib/CodeGen/AtomicExpandPass.cpp
    M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
    M llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
    M llvm/lib/IR/Core.cpp
    M llvm/lib/IR/Instructions.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineAtomicRMW.cpp
    M llvm/lib/Transforms/Utils/LowerAtomic.cpp
    M llvm/test/Assembler/atomic.ll
    M llvm/test/Bitcode/compatibility.ll
    M llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
    M llvm/test/Transforms/InstCombine/atomicrmw.ll
    M llvm/test/Transforms/LowerAtomic/atomic-load.ll

  Log Message:
  -----------
  [LLVM] Add the support for fmax and fmin in atomicrmw instruction

This patch adds the support for `fmax` and `fmin` operations in `atomicrmw`
instruction. For now (at least in this patch), the instruction will be expanded
to CAS loop. There are already a couple of targets supporting the feature. I'll
create another patch(es) to enable them accordingly.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D127041