[all-commits] [llvm/llvm-project] d1af09: [AMDGPU] gfx11 Generate VOPD Instructions

[Joe Nash via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1af09ad9617c389180869d4f47d562d4e29f700
      https://github.com/llvm/llvm-project/commit/d1af09ad9617c389180869d4f47d562d4e29f700
  Author: Joe Nash <Joseph.Nash at amd.com>
  Date:   2022-07-05 (Tue, 05 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPU.h
    M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
    M llvm/lib/Target/AMDGPU/CMakeLists.txt
    A llvm/lib/Target/AMDGPU/GCNCreateVOPD.cpp
    A llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
    A llvm/lib/Target/AMDGPU/GCNVOPDUtils.h
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
    M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
    M llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
    M llvm/test/CodeGen/AMDGPU/build_vector.ll
    M llvm/test/CodeGen/AMDGPU/clamp.ll
    M llvm/test/CodeGen/AMDGPU/cluster_stores.ll
    M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
    M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
    M llvm/test/CodeGen/AMDGPU/gfx11-user-sgpr-init16-bug.ll
    M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx11.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.intersect_ray.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp8.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane64.ll
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sendmsg.rtn.ll
    M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
    M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
    M llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-global-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-agent.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-singlethread.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-system.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-wavefront.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-local-workgroup.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
    M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
    A llvm/test/CodeGen/AMDGPU/verify-vopd.mir
    A llvm/test/CodeGen/AMDGPU/vopd-combine.mir
    M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll

  Log Message:
  -----------
  [AMDGPU] gfx11 Generate VOPD Instructions

We form VOPD  instructions in the GCNCreateVOPD pass by combining
back-to-back component instructions. There are strict register
constraints for creating a legal VOPD, namely that the matching operands
(e.g. src0x and src0y, src1x and src1y) must be in different register
banks. We add a PostRA scheduler
mutation to put possible VOPD components back-to-back.

Depends on D128442, D128270

Reviewed By: #amdgpu, rampitec

Differential Revision: https://reviews.llvm.org/D128656