[all-commits] [llvm/llvm-project] c06d0b: [RISCV] Add ADDI instr for computing FrameIndex ad...

luxufan via All-commits all-commits at lists.llvm.org
Mon Jul 4 07:14:12 PDT 2022 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c06d0b4d02ea9ab66f3ef75286d4263594336368
      https://github.com/llvm/llvm-project/commit/c06d0b4d02ea9ab66f3ef75286d4263594336368
  Author: luxufan <luxufan at iscas.ac.cn>
  Date:   2022-07-04 (Mon, 04 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
    M llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
    M llvm/test/CodeGen/RISCV/rvv/localvar.ll
    M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
    M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll
    M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll
    M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
    M llvm/test/CodeGen/RISCV/rvv/vaadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vaaddu.ll
    M llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vadd.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vasub.ll
    M llvm/test/CodeGen/RISCV/rvv/vasubu.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vmul.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulh.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
    M llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vrsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vsub.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
    M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

  Log Message:
  -----------
  [RISCV] Add ADDI instr for computing FrameIndex address

RVV doesn't have immediate field for memory addressing. Currently
we build MachineInstructions in PEI to computing stack offset for
RVV load store instructions. These instructions were added too late to
can be optimized by CSE, LICM... passes.

This patch makes FrameIndex SDNodes can't be matched in RVV Load Store
instruction selection patterns. So that the FrameIndex SDNodes would be
selected as `ADDI GPR, targetframeindex`.

There are 2 advantages for such change:
1. Stack objects address computing can be optimized by machine function
passes.
2. Since the ADDI instruction's destination register can be used as a
temp register, we can save an emergency spill slot.

Differential Revision: https://reviews.llvm.org/D128187

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