[all-commits] [llvm/llvm-project] 0f45ea: [RISCV] Add a scavenge spill slot when use ADDI to...

[luxufan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0f45eaf0da1f28a744f7dd24536e6d1a25b7d6cf
      https://github.com/llvm/llvm-project/commit/0f45eaf0da1f28a744f7dd24536e6d1a25b7d6cf
  Author: luxufan <luxufan at iscas.ac.cn>
  Date:   2022-07-03 (Sun, 03 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfo.h
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    A llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
    M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
    M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll

  Log Message:
  -----------
  [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset

Computing scalable offset needs up to two scrach registers. We add
scavenge spill slots according to the result of `RISCV::isRVVSpill`
and `RVVStackSize`. Since ADDI is not included in `RISCV::isRVVSpill`,
PEI doesn't add scavenge spill slots for scrach registers when using
ADDI to get scalable stack offsets.

The ADDI instruction has a destination register which can be used as
a scrach register. So one scavenge spil slot is sufficient for
computing scalable stack offsets.

Differential Revision: https://reviews.llvm.org/D128188