[all-commits] [llvm/llvm-project] 7e4ab9: [RISCV] Add more SHXADD isel patterns.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7e4ab9d5b8b855602c602fe0908afcf078ce3f20
      https://github.com/llvm/llvm-project/commit/7e4ab9d5b8b855602c602fe0908afcf078ce3f20
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-02 (Sat, 02 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] Add more SHXADD isel patterns.

This handles the code we get for

int foo(int* x, unsigned y) {
  return x[y >> 1];
}

The shift right and the shl will get DAG combined into
(shl (and X, 0xfffffffe), 1). We have custom isel to match the
shl+and, but with Zba the (add (shl X, 1), Y) part will get
matched and leave the and to be iseled by itself. This commit
adds a larger pattern that includes the and.