[all-commits] [llvm/llvm-project] 5d7876: [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d787689b14574fe58ba9798563f4a6df6059fbf
      https://github.com/llvm/llvm-project/commit/5d787689b14574fe58ba9798563f4a6df6059fbf
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-02 (Sat, 02 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Match RISCVISD::ADD_LO in SelectAddrRegImm.

This allows us to fold global and constant pool addresses into
load/store during isel instead of in the post-isel peephole. I
did not copy the alignment check for ConsantPoolSDNode because it
wasn't tested.

This is a step towards being able to remove the post-isel
peephole.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D128738