[all-commits] [llvm/llvm-project] 690db1: [AArch64] Make nxv1i1 types a legal type for SVE.

[sdesmalen-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 690db164226fb1d454c5e592726a8bc0de16c6b5
      https://github.com/llvm/llvm-project/commit/690db164226fb1d454c5e592726a8bc0de16c6b5
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2022-07-01 (Fri, 01 Jul 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/Target/AArch64/AArch64CallingConvention.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/lib/Target/AArch64/SVEInstrFormats.td
    M llvm/test/CodeGen/AArch64/sve-extract-scalable-vector.ll
    M llvm/test/CodeGen/AArch64/sve-select.ll
    M llvm/test/CodeGen/AArch64/sve-zeroinit.ll

  Log Message:
  -----------
  [AArch64] Make nxv1i1 types a legal type for SVE.

One motivation to add support for these types are the LD1Q/ST1Q
instructions in SME, for which we have defined a number of load/store
intrinsics which at the moment still take a `<vscale x 16 x i1>` predicate
regardless of their element type.

This patch adds basic support for the nxv1i1 type such that it can be passed/returned
from functions, as well as some basic support to support some existing tests that
result in a nxv1i1 type. It also adds support for splats.

Other operations (e.g. insert/extract subvector, logical ops, etc) will be
supported in follow-up patches.

Reviewed By: paulwalker-arm, efriedma

Differential Revision: https://reviews.llvm.org/D128665