[all-commits] [llvm/llvm-project] 516634: [SVE][AArch64] Refine hasSVEArgsOrReturn

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5166345f50412f1a380948c18809545c4b7a9bd3
      https://github.com/llvm/llvm-project/commit/5166345f50412f1a380948c18809545c4b7a9bd3
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2022-07-01 (Fri, 01 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
    M llvm/lib/Target/AArch64/AArch64RegisterInfo.h
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll

  Log Message:
  -----------
  [SVE][AArch64] Refine hasSVEArgsOrReturn

As described in aapcs64 (https://github.com/ARM-software/abi-aa/blob/2022Q1/aapcs64/aapcs64.rst#scalable-vector-registers)
AAVPCS is used only when registers z0-z7 take an SVE argument. This fixes the case where floats occupy the lower bits
of registers z0-z7 but SVE arguments in registers greater than z7 cause a function to use AAVPCS where it should use AAPCS.

Moving SVE function deduction from AArch64RegisterInfo::hasSVEArgsOrReturn to AArch64TargetLowering::LowerFormalArguments
where physical register lowering is more accurate fixes this.

Differential Revision: https://reviews.llvm.org/D127209