[all-commits] [llvm/llvm-project] 5fe5aa: [ISel] Match all bits when merge undef(s) for DAG ...

[xiangzh1 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fe5aa284efed1ee1492e1f266351b35f0a8bb69
      https://github.com/llvm/llvm-project/commit/5fe5aa284efed1ee1492e1f266351b35f0a8bb69
  Author: Xiang1 Zhang <xiang1.zhang at intel.com>
  Date:   2022-07-01 (Fri, 01 Jul 2022)

  Changed paths:
    M llvm/include/llvm/ADT/APInt.h
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/lib/Support/APInt.cpp
    M llvm/test/CodeGen/X86/fshl-splat-undef.ll
    M llvm/unittests/ADT/APIntTest.cpp

  Log Message:
  -----------
  [ISel] Match all bits when merge undef(s) for DAG combine