[all-commits] [llvm/llvm-project] 354e04: [RISCV] Make custom isel for (add X, imm) used by ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 354e04554a35c1007c7bbf0c7477bdea08642cfc
      https://github.com/llvm/llvm-project/commit/354e04554a35c1007c7bbf0c7477bdea08642cfc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-30 (Thu, 30 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/mem64.ll

  Log Message:
  -----------
  [RISCV] Make custom isel for (add X, imm) used by load/stores more selective.

Only handle immediates that would produce an ADDI or ADDIW of Lo12
as the final instruction in their materialization.

As the test change show this removes immediates that materialize
with lui+addiw that is not the same as lui+addi.