[all-commits] [llvm/llvm-project] 781e3d: [RISCV] Pre-commit tests for D128869. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 781e3d7ad82c30656e204ecec4635079807e41bd
      https://github.com/llvm/llvm-project/commit/781e3d7ad82c30656e204ecec4635079807e41bd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-30 (Thu, 30 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

  Log Message:
  -----------
  [RISCV] Pre-commit tests for D128869. NFC


  Commit: 9ace5af0495c9142d728e9e48073d4de521f0f6d
      https://github.com/llvm/llvm-project/commit/9ace5af0495c9142d728e9e48073d4de521f0f6d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-30 (Thu, 30 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

  Log Message:
  -----------
  [RISCV] DAG combine (sra (shl X, 32), 32 - C) -> (shl (sext_inreg X, i32), C).

The sext_inreg can often be folded into an earlier instruction by
using a W instruction. The sext_inreg also works better with our ABI.

This is one of the steps to improving the generated code for this https://godbolt.org/z/hssn6sPco

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128843


  Commit: 51d672946efdfacc06948cd46b51109b07ac12e5
      https://github.com/llvm/llvm-project/commit/51d672946efdfacc06948cd46b51109b07ac12e5
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-30 (Thu, 30 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64i-shift-sext.ll

  Log Message:
  -----------
  [RISCV] Fold (sra (add (shl X, 32), C1), 32 - C) -> (shl (sext_inreg (add X, C1), C)

Similar for a subtract with a constant left hand side.

(sra (add (shl X, 32), C1<<32), 32) is the canonical IR from InstCombine
for (sext (add (trunc X to i32), 32) to i32).

For RISCV, we should lower this as addiw which means turning it into
(sext_inreg (add X, C1)).

There is an existing DAG combine to convert back to (sext (add (trunc X
to i32), 32) to i32), but it requires isTruncateFree to return true
and for i32 to be a legal type as it used sign_extend and truncate
nodes. So that doesn't work for RISCV.

If the outer sra happens be used by a shl by constant, it will be
folded and the shift amount of the sra will be changed before we
can do our own DAG combine. This requires us to match the more
general pattern and restore the shl.

I had wanted to do this as a separate (add (shl X, 32), C1<<32) ->
(shl (add X, C1), 32) combine, but that hit an infinite loop for some
values of C1.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128869


Compare: https://github.com/llvm/llvm-project/compare/21f1dca125bc...51d672946efd