[all-commits] [llvm/llvm-project] 7cbfb4: [RISCV] Select (srl (and X, C2) as (slli (srliw X, ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7cbfb4eb7a9e24ede4a59e9c08d91747d8475e03
      https://github.com/llvm/llvm-project/commit/7cbfb4eb7a9e24ede4a59e9c08d91747d8475e03
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-29 (Wed, 29 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/copysign-casts.ll
    M llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

  Log Message:
  -----------
  [RISCV] Select (srl (and X, C2) as (slli (srliw X, C3), C3-C).

If C2 has 32 leading zeros and C3 trailing zeros.