[all-commits] [llvm/llvm-project] 3ea812: AMDGPU: Add more rematerialization tests for 16-bi...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3ea812bb1b868d86782db5b5c353b1df7b298b44
      https://github.com/llvm/llvm-project/commit/3ea812bb1b868d86782db5b5c353b1df7b298b44
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-06-29 (Wed, 29 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir

  Log Message:
  -----------
  AMDGPU: Add more rematerialization tests for 16-bit instructions


  Commit: da6d7728d489c6b8bc4cf1cde70100867cf693bc
      https://github.com/llvm/llvm-project/commit/da6d7728d489c6b8bc4cf1cde70100867cf693bc
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-06-29 (Wed, 29 Jun 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/VOP2Instructions.td
    M llvm/test/CodeGen/AMDGPU/remat-vop.mir

  Log Message:
  -----------
  AMDGPU: Mark more instructions as rematerializable

D106023 excluded 16-bit instructions from rematerialization, with the
justification that we can't rematerialize instructions that preserve
the high bits (plus the instructions which do are a confusing mess
between different subtargets). This doesn't make sense to me as a
problem since cases where we would rely on the high bit behavior would
still need to be represented as a register value constraint with a
tied operand. It's not a hidden side effect and should still be
rematerializable.


Compare: https://github.com/llvm/llvm-project/compare/bdba8278d9c3...da6d7728d489