[all-commits] [llvm/llvm-project] 5cb097: [X86][AMX] Split greedy RA for tile register

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cb09798700aecff1f9f61b7cd80852c61e10fa8
      https://github.com/llvm/llvm-project/commit/5cb09798700aecff1f9f61b7cd80852c61e10fa8
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2022-06-29 (Wed, 29 Jun 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetPassConfig.h
    M llvm/lib/CodeGen/TargetPassConfig.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.cpp
    M llvm/lib/Target/X86/X86RegisterInfo.h
    M llvm/lib/Target/X86/X86TargetMachine.cpp
    M llvm/lib/Target/X86/X86TileConfig.cpp
    M llvm/test/CodeGen/X86/AMX/amx-across-func.ll
    A llvm/test/CodeGen/X86/AMX/amx-greedy-ra-spill-shape.ll
    A llvm/test/CodeGen/X86/AMX/amx-greedy-ra.ll
    M llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll
    M llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll
    M llvm/test/CodeGen/X86/opt-pipeline.ll
    M llvm/test/CodeGen/X86/statepoint-ra.ll

  Log Message:
  -----------
  [X86][AMX] Split greedy RA for tile register

When we fill the shape to tile configure memory, the shape is gotten
from AMX pseudo instruction. However the register for the shape may be
split or spilled by greedy RA. That cause we fill the shape to config
memory after ldtilecfg is executed, so that the shape configuration
would be wrong.
This patch is to split the tile register allocation from greedy register
allocation, so that after tile registers are allocated the shape
registers are still virtual register. The shape register only may be
redefined or multi-defined by phi elimination pass, two address pass.
That doesn't affect tile register configuration.

Differential Revision: https://reviews.llvm.org/D128584