[all-commits] [llvm/llvm-project] 8871c3: [AMDGPU] Regenerate MIR checks. NFC.

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8871c3c562690347d75190be758312d1f92a7db4
      https://github.com/llvm/llvm-project/commit/8871c3c562690347d75190be758312d1f92a7db4
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-add-nullptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-lshr-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.postlegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-from-extend-narrow.prelegal.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shl-narrow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-zext-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.groupstaticsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-lshr.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-xor3.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrmask.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptrtoint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-returnaddress.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sbfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext-inreg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.rsq.clamp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.workitem.id.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg-with-success.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomic-cmpxchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-add.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-and.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-max.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-min.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-or.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-sub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitreverse.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-block-addr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fconstant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s16.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s32.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmad.s64.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-frint.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-amdgcn-fdiv-fast.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.s.buffer.load.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant-32bit.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
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    M llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
    M llvm/test/CodeGen/AMDGPU/regcoalescer-resolve-lane-conflict-by-subranges.mir
    M llvm/test/CodeGen/AMDGPU/remat-sop.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-gpr-idx-mode.mir
    M llvm/test/CodeGen/AMDGPU/remove-short-exec-branches-special-instructions.mir
    M llvm/test/CodeGen/AMDGPU/return-with-successors.mir
    M llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
    M llvm/test/CodeGen/AMDGPU/schedule-barrier-fpmode.mir
    M llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
    M llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
    M llvm/test/CodeGen/AMDGPU/shrink-instructions-flags.mir
    M llvm/test/CodeGen/AMDGPU/shrink-insts-scalar-bit-ops.mir
    M llvm/test/CodeGen/AMDGPU/si-i1-copies.mir
    M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
    M llvm/test/CodeGen/AMDGPU/skip-branch-taildup-ret.mir
    M llvm/test/CodeGen/AMDGPU/soft-clause-dbg-value.mir
    M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
    M llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
    M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
    M llvm/test/CodeGen/AMDGPU/swdev282079.mir
    M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
    M llvm/test/CodeGen/AMDGPU/unallocatable-bundle-regression.mir
    M llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
    M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
    M llvm/test/CodeGen/AMDGPU/vgpr-spill.mir
    M llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
    M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir

  Log Message:
  -----------
  [AMDGPU] Regenerate MIR checks. NFC.