[all-commits] [llvm/llvm-project] fadea4: [NFC][SVE] Auto-generate CHECK lines for intrinsic...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: fadea4413ecbfffa4d28ad8298e0628165b543f1
      https://github.com/llvm/llvm-project/commit/fadea4413ecbfffa4d28ad8298e0628165b543f1
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-06-27 (Mon, 27 Jun 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/sve-intrinsics-adr.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-bfloat.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-conversion.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-counting-bits.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-dup-x.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-vector-base-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ff-gather-loads-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-loads-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-scalar-base-vector-indexes.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-gather-prefetches-vect-base-invalid-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-insert-extract-tuple.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares-with-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-int-compares.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-reg+reg-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-ff.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-logical.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-fp32.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-fp64.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-matmul-int8.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select-matmul-fp64.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-pred-creation.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-pred-testing.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-reversal.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-scaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base-imm-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-scatter-stores-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts-merging.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-shifts.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-sqdec.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-sqinc.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-st1.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-reg-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stores.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-unpred-form.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-uqdec.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-uqinc.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-while.ll
    M llvm/test/CodeGen/AArch64/sve-vselect-imm.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-add-sub.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-binary-narrowing-shr.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-bit-permutation.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-character-match.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-complex-dot.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-crypto.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-int-binary-logarithm.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-widening-mul-acc.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-non-widening-pairwise-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-32bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-gather-loads-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores-32bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores-64bit-scaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores-64bit-unscaled-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-nt-scatter-stores-vector-base-scalar-offset.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic-128.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-polynomial-arithmetic.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-unary-narrowing.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-complex-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-zeroing.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-vec-hist-count.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-while.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-complex-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-dsp.ll
    M llvm/test/CodeGen/AArch64/sve2-intrinsics-widening-pairwise-arith.ll

  Log Message:
  -----------
  [NFC][SVE] Auto-generate CHECK lines for intrinsic codegen tests.