[all-commits] [llvm/llvm-project] 66a6c1: [libc] Add a cacheline size of arm target.

Siva Chandra via All-commits all-commits at lists.llvm.org
Fri Jun 24 21:46:22 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66a6c1073a204de5729e0ec82508697aeb08bcf1
  Author: Siva Chandra Reddy <sivachandra at google.com>
  Date:   2022-06-25 (Sat, 25 Jun 2022)

  Changed paths:
    M libc/src/string/memory_utils/utils.h

  Log Message:
  [libc] Add a cacheline size of arm target.

It is set arbitrarily at 32 now. It can be adjusted as required in

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