[all-commits] [llvm/llvm-project] 78a31b: [RISCV] Change how we isel (add X, [-4096, -2049])...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78a31bb96961b30222f96d45b589bad7bc957cb4
      https://github.com/llvm/llvm-project/commit/78a31bb96961b30222f96d45b589bad7bc957cb4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-24 (Fri, 24 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/test/CodeGen/RISCV/add-imm.ll
    M llvm/test/CodeGen/RISCV/addimm-mulimm.ll
    M llvm/test/CodeGen/RISCV/xaluo.ll

  Log Message:
  -----------
  [RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).

We currently split the immediate almost equally between two addis.
If the immediate is odd, it won't be split exactly equal.

This patch instead gives one addi an immediate of 2047 or -2048 and the
other getsthe remainder. If the original immediate is near -2049 or 2048,
this might allow the use of c.addi for the addi that receives the
smaller immediate.

Reviewed By: asb, luismarques

Differential Revision: https://reviews.llvm.org/D128500