[all-commits] [llvm/llvm-project] 78a31b: [RISCV] Change how we isel (add X, [-4096, -2049])...
Craig Topper via All-commits
all-commits at lists.llvm.org
Fri Jun 24 08:32:16 PDT 2022
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-06-24 (Fri, 24 Jun 2022)
[RISCV] Change how we isel (add X, [-4096, -2049]) or (add X, [2048,4095]).
We currently split the immediate almost equally between two addis.
If the immediate is odd, it won't be split exactly equal.
This patch instead gives one addi an immediate of 2047 or -2048 and the
other getsthe remainder. If the original immediate is near -2049 or 2048,
this might allow the use of c.addi for the addi that receives the
Reviewed By: asb, luismarques
Differential Revision: https://reviews.llvm.org/D128500
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