[all-commits] [llvm/llvm-project] c579ab: [RISCV] Move vfma_vl+fneg_vl matching to DAG combine.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c579ab53bd4ad8563fb9ae3b3e0267c3a51b27d9
      https://github.com/llvm/llvm-project/commit/c579ab53bd4ad8563fb9ae3b3e0267c3a51b27d9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-24 (Fri, 24 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

  Log Message:
  -----------
  [RISCV] Move vfma_vl+fneg_vl matching to DAG combine.

This patch adds 3 new _VL RISCVISD opcodes to represent VFMA_VL with
different portions negated. It also adds a DAG combine to peek
through FNEG_VL to create these new opcodes.

This is modeled after similar code from X86.

This makes the isel patterns more regular and reduces the size of
the isel table by ~37K.

The test changes look like regressions, but they point to a bug that
was already there. We aren't able to commute a masked FMA instruction
to improve register allocation because we always use a mask undisturbed
policy. Prior to this patch we matched two multiply operands in a
different order and hid this issue for these test cases, but a different
test still could have encountered it.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D128310