[all-commits] [llvm/llvm-project] 8b10ff: [RISCV] Disable <vscale x 1 x *> types with Zve32x...
Craig Topper via All-commits
all-commits at lists.llvm.org
Thu Jun 23 08:49:40 PDT 2022
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-06-23 (Thu, 23 Jun 2022)
[RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.
According to the vector spec, mf8 is not supported for i8 if ELEN
is 32. Similarily mf4 is not suported for i16/f16 or mf2 for i32/f32.
Since RVVBitsPerBlock is 64 and LMUL is calculated as
((MinNumElements * ElementSize) / RVVBitsPerBlock) this means we
need to disable any type with MinNumElements==1.
For generic IR, these types will now be widened in type legalization.
For RVV intrinsics, we'll probably hit a fatal error somewhere. I plan
to work on disabling the intrinsics in the riscv_vector.h header.
Reviewed By: arcbbb
Differential Revision: https://reviews.llvm.org/D128286
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