[all-commits] [llvm/llvm-project] 8b10ff: [RISCV] Disable <vscale x 1 x *> types with Zve32x...

Craig Topper via All-commits all-commits at lists.llvm.org
Thu Jun 23 08:49:40 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b10ffabae48ae6eae5ece711c13b93f9c232515
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-23 (Thu, 23 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    A llvm/test/CodeGen/RISCV/rvv/zve32-types.ll

  Log Message:
  [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.

According to the vector spec, mf8 is not supported for i8 if ELEN
is 32. Similarily mf4 is not suported for i16/f16 or mf2 for i32/f32.

Since RVVBitsPerBlock is 64 and LMUL is calculated as
((MinNumElements * ElementSize) / RVVBitsPerBlock) this means we
need to disable any type with MinNumElements==1.

For generic IR, these types will now be widened in type legalization.
For RVV intrinsics, we'll probably hit a fatal error somewhere. I plan
to work on disabling the intrinsics in the riscv_vector.h header.

Reviewed By: arcbbb

Differential Revision: https://reviews.llvm.org/D128286

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