[all-commits] [llvm/llvm-project] 16d3a8: [RISCV] Add merge operand to RISCVISD::VRGATHER*_V...
Craig Topper via All-commits
all-commits at lists.llvm.org
Mon Jun 20 19:16:54 PDT 2022
Author: Craig Topper <craig.topper at sifive.com>
Date: 2022-06-20 (Mon, 20 Jun 2022)
[RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.
Use it in place of VSELECT_VL+VRGATHER*_VL.
This simplifies the isel patterns.
Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D128023
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