[all-commits] [llvm/llvm-project] 16d3a8: [RISCV] Add merge operand to RISCVISD::VRGATHER*_V...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 16d3a82de53dab4bb5ed468aff92df276f8a6e39
      https://github.com/llvm/llvm-project/commit/16d3a82de53dab4bb5ed468aff92df276f8a6e39
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

  Log Message:
  -----------
  [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes.

Use it in place of VSELECT_VL+VRGATHER*_VL.

This simplifies the isel patterns.

Overall, I think trying to match select+op to create masked instructions
in isel doesn't scale. We either need to do it in DAG combine, pre-isel
peepole, or post-isel peephole. I don't yet know which is the right
answer, but for this case it seemed best to be able to request the
masked form directly from lowering.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D128023