[all-commits] [llvm/llvm-project] 44e8a2: [fastregalloc] Enhance the heuristics for liveout ...

[Luo, Yuanke via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 44e8a205f4cf747b920726428ee9e35c2ac3d706
      https://github.com/llvm/llvm-project/commit/44e8a205f4cf747b920726428ee9e35c2ac3d706
  Author: Luo, Yuanke <yuanke.luo at intel.com>
  Date:   2022-06-21 (Tue, 21 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/RegAllocFast.cpp
    M llvm/test/CodeGen/AArch64/atomicrmw-O0.ll
    M llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
    M llvm/test/CodeGen/X86/atomic32.ll
    M llvm/test/CodeGen/X86/atomic64.ll
    M llvm/test/CodeGen/X86/atomic6432.ll
    M llvm/test/CodeGen/X86/fastregalloc-selfloop.mir
    M llvm/test/CodeGen/X86/swifterror.ll
    M llvm/test/DebugInfo/X86/fission-ranges.ll

  Log Message:
  -----------
  [fastregalloc] Enhance the heuristics for liveout in self loop.

For below case, virtual register is defined twice in the self loop. We
don't need to spill %0 after the third instruction `%0 = def (tied %0)`,
because it is defined in the second instruction `%0 = def`.

1 bb.1
2 %0 = def
3 %0 = def (tied %0)
4 ...
5 jmp bb.1

Reviewed By: MatzeB

Differential Revision: https://reviews.llvm.org/D125079