[all-commits] [llvm/llvm-project] c0ecbf: [AArch64] Known bits for AArch64ISD::DUP

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c0ecbfa4fdf0906745679c1262b08dc4cdbb5537
      https://github.com/llvm/llvm-project/commit/c0ecbfa4fdf0906745679c1262b08dc4cdbb5537
  Author: David Green <david.green at arm.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/test/CodeGen/AArch64/arm64-build-vector.ll
    M llvm/test/CodeGen/AArch64/arm64-sli-sri-opt.ll

  Log Message:
  -----------
  [AArch64] Known bits for AArch64ISD::DUP

An AArch64ISD::DUP is just a splat, where the known bits for each lane
are the same as the input. This teaches that to computeKnownBitsForTargetNode.

Problems arise for constants though, as a constant BUILD_VECTOR can be
lowered to an AArch64ISD::DUP, which SimplifyDemandedBits would then
turn back into a constant BUILD_VECTOR leading to an infinite cycle.
This has been prevented by adding a isTargetCanonicalConstantNode node
to prevent the conversion back into a BUILD_VECTOR.

Differential Revision: https://reviews.llvm.org/D128144