[all-commits] [llvm/llvm-project] 013358: [AArch64][SME] Add the zero intrinsic

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 013358632e657f3138f055313ef7b51cbafe06ce
      https://github.com/llvm/llvm-project/commit/013358632e657f3138f055313ef7b51cbafe06ce
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/SMEInstrFormats.td
    A llvm/test/CodeGen/AArch64/sme-intrinsics-zero.ll

  Log Message:
  -----------
  [AArch64][SME] Add the zero intrinsic

The SME zero instruction takes a mask as an input declaring which
64-bit element tiles should be zeroed. There is a 1:1 mapping
between the zero intrinsic and the instruction, however we also
want to make the register allocator aware that some tile
registers are being written to.

We can actually just use the custom inserter for a pseudo instruction
to correctly mark all the appropriate registers in the mask as
implicitly defined by the operation.

 Differential Revision: https://reviews.llvm.org/D127843