[all-commits] [llvm/llvm-project] 314dbd: [DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceS...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 314dbde12cd2ae2809cbba6de0504b034a289a40
      https://github.com/llvm/llvm-project/commit/314dbde12cd2ae2809cbba6de0504b034a289a40
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-19 (Sun, 19 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
    A llvm/test/CodeGen/RISCV/pr56110.ll

  Log Message:
  -----------
  [DAGCombiner][ARM][RISCV] Teach ShrinkLoadReplaceStoreWithStore to use truncstore.

The VT we want to shrink to may not be legal especially after type
legalization.

Fixes PR56110.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D128135