[all-commits] [llvm/llvm-project] db1be6: [DAG] SimplifyDemandedBits - add ISD::VSELECT hand...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: db1be696c406fd4e894883845eea2f030e992626
      https://github.com/llvm/llvm-project/commit/db1be696c406fd4e894883845eea2f030e992626
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-06-19 (Sun, 19 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    M llvm/test/CodeGen/Hexagon/isel-memory-vNi1.ll
    M llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
    M llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
    M llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll
    M llvm/test/CodeGen/X86/extractelement-load.ll
    M llvm/test/CodeGen/X86/known-signbits-vector.ll
    M llvm/test/CodeGen/X86/select-of-fp-constants.ll
    M llvm/test/CodeGen/X86/vselect-zero.ll

  Log Message:
  -----------
  [DAG] SimplifyDemandedBits - add ISD::VSELECT handling