[all-commits] [llvm/llvm-project] 545a71: [RISCV] Pre-promote v1i1/v2i1/v4i1->i1/i2/i4 bitca...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 545a71c0d66eb93eb47ad49ec6f91965cca8f137
      https://github.com/llvm/llvm-project/commit/545a71c0d66eb93eb47ad49ec6f91965cca8f137
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-18 (Sat, 18 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

  Log Message:
  -----------
  [RISCV] Pre-promote v1i1/v2i1/v4i1->i1/i2/i4 bitcasts before type legalization

Type legalization will convert the bitcast into a vector store and
scalar load.

Instead this patch widens the vector to v8i1 with undef, and bitcasts
it to i8. v8i1->i8 has custom handling for type legalization already to
bitcast to a v1i8 vector and use an extract_element.

The code here was lifted from X86's avx512 support.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D128099