[all-commits] [llvm/llvm-project] 5afdce: [RISCV] Add RISCVISD opcode for PseudoLLA.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5afdceb82b9296ab95ff57c54913354e74a0da02
      https://github.com/llvm/llvm-project/commit/5afdceb82b9296ab95ff57c54913354e74a0da02
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  -----------
  [RISCV] Add RISCVISD opcode for PseudoLLA.

Rather than emitting a MachineSDNode from lowering. Let isel match it.

This is consistent with the RISCVISD::HI and ADD_LO nodes that were
also added. Having them both the same will make D127679 consistent.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127714


  Commit: 9d7b01dc9521f4385eb8bbc80f99652f373e520b
      https://github.com/llvm/llvm-project/commit/9d7b01dc9521f4385eb8bbc80f99652f373e520b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll
    M llvm/test/CodeGen/RISCV/rv64zbp.ll

  Log Message:
  -----------
  [RISCV] Implement RISCVTargetLowering::getTargetConstantFromLoad.

This allows computeKnownBits to see the constant being loaded.

This recovers the rv64zbp test case changes from D127520.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D127679


Compare: https://github.com/llvm/llvm-project/compare/ee28837a1fbd...9d7b01dc9521