[all-commits] [llvm/llvm-project] e6c7a3: [SelectionDAG] Don't apply MinRCSize constraint in...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e6c7a3a54ffaf0001017f619faf2fa260fb517b4
      https://github.com/llvm/llvm-project/commit/e6c7a3a54ffaf0001017f619faf2fa260fb517b4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    A llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll

  Log Message:
  -----------
  [SelectionDAG] Don't apply MinRCSize constraint in InstrEmitter::AddRegisterOperand for IMPLICIT_DEF sources.

MinRCSize is 4 and prevents constrainRegClass from changing the
register class if the new class has size less than 4.

IMPLICIT_DEF gets a unique vreg for each use and will be removed
by the ProcessImplicitDef pass before register allocation. I don't
think there is any reason to prevent constraining the virtual register
to whatever register class the use needs.

The attached test case was previously creating a copy of IMPLICIT_DEF
because vrm8nov0 has 3 registers in it.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D128005