[all-commits] [llvm/llvm-project] a9dccb: [TargetTransformInfo] Added an opt/llc option for ...

[CongzheUalberta via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a9dccb0072af5bd1704a6e364864f8c0e0d02d62
      https://github.com/llvm/llvm-project/commit/a9dccb0072af5bd1704a6e364864f8c0e0d02d62
  Author: Congzhe Cao <congzhe.cao at huawei.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/Analysis/TargetTransformInfo.cpp
    M llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
    A llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
    M llvm/test/CodeGen/PowerPC/ppc64-get-cache-line-size.ll

  Log Message:
  -----------
  [TargetTransformInfo] Added an opt/llc option for cache line size

In some passes we need a valid number of cache line size to do analysis or
transformation, e.g., loop cache analysis and loop date prefetch. However,
for some backend targets, `TTIImpl->getCacheLineSize()` is not implemented
and hence 'TTI.getCacheLineSize()' would just return 0 which eventually might
produce invalid result.

In this patch we add a user-specified opt/llc option for cache line size.
If the option is specified by users we use the value supplied, otherwise we
fall-back to the default value obtained from `TTIImpl->->getCacheLineSize()`.
The powerpc target already has such an option, this patch generalizes
this option to TargetTransformInfo.cpp.

Reviewed By: bmahjour, #loopoptwg

Differential Revision: https://reviews.llvm.org/D127342