[all-commits] [llvm/llvm-project] 553118: Allow bitwidth difference when checking for isOneO...

[adriantong1024 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 55311801f06d33a71deae80209dd5640d5e7463e
      https://github.com/llvm/llvm-project/commit/55311801f06d33a71deae80209dd5640d5e7463e
  Author: Adrian Tong <adriantong1024 at gmail.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    M llvm/test/CodeGen/AArch64/add-negative.ll
    M llvm/test/CodeGen/AArch64/minmax.ll

  Log Message:
  -----------
  Allow bitwidth difference when checking for isOneOrOneSplat.

This helps handling a case where the BUILD_VECTOR has i16 element type
and i32 constant operands

t2: v8i16 = setcc t8, t17, setult:ch
t3: v8i16 = BUILD_VECTOR Constant:i32<1>, ...
   t4: v8i16 = and t2, t3
      t5: v8i16 = add t8, t4

This can be turned into t5: v8i16 = sub t8, t2, and allows us to remove
t3 and t4 from the DAG.

Differential Revision: https://reviews.llvm.org/D127354