[all-commits] [llvm/llvm-project] 6f6fa5: [AArch64][SME] Add SME cntsb/h/w/d intrinsics

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6f6fa5aa10d3c0a71a897e17bd228aa9b22f9e01
      https://github.com/llvm/llvm-project/commit/6f6fa5aa10d3c0a71a897e17bd228aa9b22f9e01
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAArch64.td
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
    A llvm/test/CodeGen/AArch64/sme-intrinsics-rdsvl.ll

  Log Message:
  -----------
  [AArch64][SME] Add SME cntsb/h/w/d intrinsics

These intrinsics return the number of elements in a streaming
vector, for example aarch64.sme.cntsw returns the number of
32-bit elements. When in streaming mode these are equivalent
to aarch64.sve.cntb/h/w/d with an input value of 1.

I have implemented these intrinsics using the rdsvl instruction
and added tests here:

  CodeGen/AArch64/SME/sme-intrinsics-rdsvl.ll

Differential Revision: https://reviews.llvm.org/D127853