[all-commits] [llvm/llvm-project] 8e16c4: Reland "[RISCV] Testcase to show wrong register al...

[Kito Cheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8e16c4db571a462f931569676871e8c407bba340
      https://github.com/llvm/llvm-project/commit/8e16c4db571a462f931569676871e8c407bba340
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    A llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir

  Log Message:
  -----------
  Reland "[RISCV] Testcase to show wrong register allocation result of subreg liveness"

This reverts commit 6a6f632b93cd3ed9e35f37c04efb12fa87038b60.

This commit will failed when EXPENSIVE_CHECKS enabled, fixed by D126048.

Differential Revision: https://reviews.llvm.org/D126047


  Commit: e9f7263b381e34b7a6857e11f874e64c9457aa24
      https://github.com/llvm/llvm-project/commit/e9f7263b381e34b7a6857e11f874e64c9457aa24
  Author: Kito Cheng <kito.cheng at sifive.com>
  Date:   2022-06-16 (Thu, 16 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SplitKit.cpp
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll
    M llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.mir

  Log Message:
  -----------
  Reland "[SplitKit] Handle early clobber + tied to def correctly"

This reverts commit 7207373e1eb0dd419b4e13a5e2d0ca146ef9544e.

We found another RISC-V bug when landing D126048, and it has been fixed
by D127642 now.

Differential Revision: https://reviews.llvm.org/D126048


Compare: https://github.com/llvm/llvm-project/compare/147f74b6ee90...e9f7263b381e