[all-commits] [llvm/llvm-project] 335e8b: [PowerPC] emit VSX instructions instead of VMX ins...

[Quinn Pham via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 335e8bf1008fff5723ba36f27350eb6d5e7f187c
      https://github.com/llvm/llvm-project/commit/335e8bf1008fff5723ba36f27350eb6d5e7f187c
  Author: Quinn Pham <Quinn.Pham at ibm.com>
  Date:   2022-06-15 (Wed, 15 Jun 2022)

  Changed paths:
    M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
    M llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll
    M llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
    M llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
    M llvm/test/CodeGen/PowerPC/build-vector-tests.ll
    M llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
    M llvm/test/CodeGen/PowerPC/crypto_bifs_be.ll
    M llvm/test/CodeGen/PowerPC/extract-and-store.ll
    M llvm/test/CodeGen/PowerPC/f128-aggregates.ll
    M llvm/test/CodeGen/PowerPC/f128-arith.ll
    M llvm/test/CodeGen/PowerPC/f128-compare.ll
    M llvm/test/CodeGen/PowerPC/f128-conv.ll
    M llvm/test/CodeGen/PowerPC/f128-fma.ll
    M llvm/test/CodeGen/PowerPC/f128-passByValue.ll
    M llvm/test/CodeGen/PowerPC/f128-rounding.ll
    M llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
    M llvm/test/CodeGen/PowerPC/float-logic-ops.ll
    M llvm/test/CodeGen/PowerPC/fp-strict-f128.ll
    M llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
    M llvm/test/CodeGen/PowerPC/load-and-splat.ll
    M llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
    M llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
    M llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
    M llvm/test/CodeGen/PowerPC/pcrel_ldst.ll
    M llvm/test/CodeGen/PowerPC/ppc64-i128-abi.ll
    M llvm/test/CodeGen/PowerPC/pr25080.ll
    M llvm/test/CodeGen/PowerPC/recipest.ll
    M llvm/test/CodeGen/PowerPC/repeated-fp-divisors.ll
    M llvm/test/CodeGen/PowerPC/sat-add.ll
    M llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
    M llvm/test/CodeGen/PowerPC/signbit-shift.ll
    M llvm/test/CodeGen/PowerPC/store_fptoi.ll
    M llvm/test/CodeGen/PowerPC/test-vector-insert.ll
    M llvm/test/CodeGen/PowerPC/toc-float.ll
    M llvm/test/CodeGen/PowerPC/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/PowerPC/vavg.ll
    M llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll
    M llvm/test/CodeGen/PowerPC/vec-itofp.ll
    M llvm/test/CodeGen/PowerPC/vec-trunc.ll
    M llvm/test/CodeGen/PowerPC/vec-trunc2.ll
    M llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
    M llvm/test/CodeGen/PowerPC/vec_constants.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
    M llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector_le.ll
    M llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
    M llvm/test/CodeGen/PowerPC/vector-ldst.ll
    M llvm/test/CodeGen/PowerPC/vector-rotates.ll
    M llvm/test/CodeGen/PowerPC/vselect-constants.ll
    M llvm/test/CodeGen/PowerPC/vsx-ldst.ll
    M llvm/test/CodeGen/PowerPC/vsx.ll
    M llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
    M llvm/test/CodeGen/PowerPC/vsx_shuffle_le.ll

  Log Message:
  -----------
  [PowerPC] emit VSX instructions instead of VMX instructions for vector loads and stores

This patch changes the PowerPC backend to generate VSX load/store instructions
for all vector loads/stores on Power8 and earlier  (LE) instead of VMX
load/store instructions. The reason for this change is because VMX instructions
require the vector to be 16-byte aligned. So, a vector load/store will fail with
VMX instructions if the vector is misaligned. Also, `gcc` generates VSX
instructions in this situation which allow for unaligned access but require a
swap instruction after loading/before storing. This is not an issue for BE
because we already emit VSX instructions since no swap is required. And this is
not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which
allow for unaligned access and do not require swaps.

This patch also delays the VSX load/store for LE combines until after
LegalizeOps to prioritize other load/store combines.

Reviewed By: #powerpc, stefanp

Differential Revision: https://reviews.llvm.org/D127309