[all-commits] [llvm/llvm-project] f096d5: [DAG] Fix SDLoc mismatch in (shl (srl x, c1), c2) ...

Simon Pilgrim via All-commits all-commits at lists.llvm.org
Wed Jun 15 03:08:15 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f096d5926ddc19030550f10589c3c219f340da6c
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-06-15 (Wed, 15 Jun 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
    M llvm/test/CodeGen/AMDGPU/load-lo16.ll
    M llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
    M llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
    M llvm/test/CodeGen/X86/combine-shl.ll
    M llvm/test/CodeGen/X86/rotate-extract.ll
    M llvm/test/CodeGen/X86/shift-mask.ll
    M llvm/test/CodeGen/X86/sse2-vector-shifts.ll

  Log Message:
  [DAG] Fix SDLoc mismatch in (shl (srl x, c1), c2) -> and(shift(x,c3)) fold

Noticed by @craig.topper on D125836 which uses a tweaked copy of the same code.

Differential Revision: https://reviews.llvm.org/D127772

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