[all-commits] [llvm/llvm-project] 9096a5: [RISCV] Teach vsetvli insertion to not insert redu...
Yeting Kuo via All-commits
all-commits at lists.llvm.org
Tue Jun 14 22:58:54 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 9096a52566cb47c513fad449acbaf83c2fb921a0
https://github.com/llvm/llvm-project/commit/9096a52566cb47c513fad449acbaf83c2fb921a0
Author: Yeting Kuo <yeting.kuo at sifive.com>
Date: 2022-06-15 (Wed, 15 Jun 2022)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
Log Message:
-----------
[RISCV] Teach vsetvli insertion to not insert redundant vsetvli right after VLEFF/VLSEGFF.
VSETVLIInfos right after VLEFF/VLSEGFF are currently unknown since they modify
VL. Unknown VSETVLIInfos make next vector operations needed to be inserted
VSET(I)VLI. Actually the next vector operation of VLEFF/VLSEGFF may not need to
be inserted VSET(I)VLI if it uses same VTYPE and the resulted vl of
VLEFF/VLSEGFF.
Take the below C code as an example,
vint8m4_t vec_src1 = vle8ff_v_i8m4(str1, &new_vl, vl);
vbool2_t mask1 = vmseq_vx_i8m4_b2(vec_src1, 0, new_vl);
vsetvli insertion adds a redundant vsetvli for that,
Assembly result:
vsetvli a2,a2,e8,m4,ta,mu
vle8ff.v v28,(a0)
csrr a3,vl ; redundant
vsetvli zero,a3,e8,m4,ta,mu ; redundant
vmseq.vi v25,v28,0
After D126794, VLEFF/VLSEGFF has a define having value of VL. The patch consider
there is a ghost vsetvli right after VLEFF/VLSEGFF. The ghost VSET(I)LIs use the
vl output of the VLEFF/VLSEGFF as its AVL and same VTYPE of the VLEFF/VLSEGFF.
The ghost vsetvli must be redundant, and we could use it to get the VSETVLIInfo
right after VLEFF/VLSEGFF.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127576
More information about the All-commits
mailing list